What is an 8 bit CPU and why I did this?
This repository provides a comprehensive design and implementation of an 8-bit CPU using SystemVerilog. It includes all necessary modules to simulate and synthesize a functional CPU. The project can be used for educational purposes, helping users understand CPU architecture and design principles through practical implementation. Additionally, the provided Vivado files facilitate testing and deployment on FPGA hardware, making it a versatile resource for both learning and practical applications.
Let’s check instruction table, format and block design:
Instruction Table:
Instruction Format:
Block Design:
File and method descriptions:
alu.sv- Purpose: Implements the Arithmetic Logic Unit (ALU) of the CPU.
- Functions: Handles basic arithmetic (add, subtract) and logic operations (and, or, xor).
control_unit.sv- Purpose: Manages the control signals based on the current instruction.
- Functions: Decodes instructions and generates appropriate control signals for other components.
datapath.sv- Purpose: Integrates all the data processing units (ALU, registers, etc.).
- Functions: Coordinates the data flow and operations within the CPU.
register_file.sv- Purpose: Defines a set of registers used to store intermediate data.
- Functions: Provides read and write access to registers for the CPU operations.
top_module.sv- Purpose: The top-level module that connects all submodules (ALU, control unit, datapath, registers).
- Functions: Integrates all components to form the complete CPU.
